A common application of flash EEPROM devices is as a mass data storage subsystem for electronic devices. Such subsystems are commonly implemented as either removable memory cards that can be inserted into multiple host systems or as non-removable embedded storage within the host system. In both implementations, the subsystem includes one or more flash devices and often a subsystem controller.
Flash EEPROM devices are composed of one or more arrays of transistor cells, each cell capable of non-volatile storage of one or more bits of data. Thus flash memory does not require power to retain the data programmed therein. Once programmed however, a cell must be erased before it can be reprogrammed with a new data value. These arrays of cells are partitioned into groups to provide for efficient implementation of read, program and erase functions. A typical flash memory architecture for mass storage arranges large groups of cells into erasable blocks. Each block is further partitioned into one or more addressable sectors that are the basic unit for read and program functions.
The subsystem controller performs a number of functions including the translation of the subsystem's logical block address (LBA) to a physical chip, block, and sector address. The controller also manages the low level flash circuit operation through a series of commands that it issues to the flash memory devices via an interface bus. Another function the controller performs is to maintain the integrity of data stored to the subsystem through various means (e.g. by using an error correction code, or ECC).
FIG. 1 shows a typical prior art flash EEPROM device's internal architecture 4000. The key features include an I/O bus 411 and control signals 412 to interface to an external controller, a memory control circuit 450 to control internal memory operations with registers for command, address and status, one or more arrays 400 of flash EEPROM cells, each array with its own row decoder (XDEC) 401 and column decoder (YDEC) 402, a group of sense amplifiers and program control circuitry (SA/PROG) 454 and a Data Register 404.
If desired, a plurality of arrays 400, together with related X decoders, Y decoders, program/verified circuitry, data registers, and the like is provided, for example as taught by U.S. Pat. No. 5,890,192; issued Mar. 30, 1999, and assigned to SanDisk Corporation, the assignee of this application, and which is hereby incorporated by reference.
The external interface I/O bus 411 and control signals 412 could be configured with the following signals:
CS—Chip Select.Used to activate flash memory interface.RS—Read Strobe.Used to indicate AD bus is being usedfor a data read operation.WS—Write Strobe.Used to indicate AD bus is being usedfor a data write operation.AS—Address Strobe.Indicates that AD bus is being usedto transfer address information.AD[7:0]—Address/Data BusUsed to transfer data between controllerand flash memory command, address anddata registers.
This interface is given only as an example as other signal configurations can be used to give the same functionality. This diagram shows only one flash memory array 400 with its related components, but a multiplicity of arrays can exist on a single flash memory chip that share a common interface and memory control circuitry but have separate XDEC, YDEC, SA/PROG and DATA REG circuitry in order to allow parallel read and program operations.
Data from the EEPROM system 4000 data register 404 to an external controller via the data registers coupling to the I/O bus AD[7:0] 411. The data register 404 is also coupled the sense amplifier/programming circuit 454. The number of elements of the data register coupled to each sense amplifier/programming circuit element may depend on the number of bits stored in each flash EEPROM cell. Each flash EEPROM cell may include a plurality of bits, such as 2 or 4, if multi-state memory cells are employed.
Row decoder 401 decodes row addresses for array 400 in order to select the physical sector being accessed. Row decoder 401 receives row addresses via internal row address lines 419 from memory control logic 450. Column decoder 402 receives column addresses via internal column address lines 429 from memory control logic 450.
FIG. 2 shows a typical flash card architecture that has a single controller 301 that performs host and memory control functions and a flash memory array that is composed of one or more flash memory devices. The system controller and the flash memory are connected by bus 302 that allows controller 301 to load command, address, and transfer data to and from the flash memory array.
It is common practice that each sector's worth of host data programmed into a sector is appended with an Error Detection and Correction Code (ECC) that is used to determine the validity of the stored data upon read back. Some such systems would use the occasion of the transfer from the memory device to the controller as an opportunity to check the validity of the data being read as a way to ensure that the data has not been corrupted.
In order to ensure the validity of the data programmed, some systems read the data from a sector immediately after it is programmed. The data is verified before the next operation proceeds by means of ECC, data comparison, or other mechanism. In prior art systems, this data verification, as it is known to those experienced in the art, occurs during the data transfer that takes place after the read. Thus there is an increase in the time to perform a program operation due to the addition of a read operation and the transfer of the data from the flash memory device to the controller circuit, where the verification is actually performed. The program verify operation indicates whether or not all cells have been programmed to or above the desired level and does not generally check if cells have over-shot the target state, possibly to the next state in the case of multi-state memory, but only if they have exceeded a particular verification condition. Due to the overall fidelity of these storage devices, the occurrence of failure during such verifications is rare.
FIG. 3 shows a timing diagram of a two-sector program/verify operation in which data is programmed into two destination addresses (DST[N] and DST[N+1]) and subsequently read in order to verify before programming to the next destination address (DST[N+2]). The READ signal indicates that a read is taking place from the source sector. The XFER signal indicates a data transfer between the flash data register and the controller. The R/WB signal indicates the direction of the transfer (high being a read from the flash to the controller and low being write from the controller to the flash). The PROG signal indicates that a program operation is taking place upon the destination page.
FIG. 4 illustrates the sequence of events that occur during a program/verify operation:                1. Transfer data to master data register 403 from external controller circuit (not shown).        2. Transfer contents of master data register 403 to slave data register 404.        3. Program the data from slave data register 404 into flash memory array 400.        4. Read back data from flash memory array 400 into slave data register 404.        5. Transfer data from slave register 404 to master data register 403.        6. Transfer data from master data register 403 to external controller circuit (not shown) for validation.        
The exact cost of these verification operations varies depending on the times of various flash memory operations, the data set size, the I/O bus size and the I/O bus cycle time. But an example using some typical values is shown below:TRD=25 μs TX=26.4 μs TPRG=300 μsThe total time to program and verify a single sector (as shown in FIG. 4).TPgm/Vfy=TX+TPRG+TRD+TX=377 μsMaking the data verification time 14% of the overall program/verify operation.
It is a general trend in non-volatile memory design to increase the number of cells that can be programmed and read at one time in order to improve the write and read performance of these devices. This can be accomplished by increasing the number of memory cell arrays on a single die, increasing the page size within a single plane, programming multiple chips in parallel or some combination of these three techniques. The result of any of these is that the data transfer length increases for the larger number of cells being programmed or read with the program and read times changing little or not at all. Thus, the expense of data verification in a system that has such increased parallelism is that much higher. As an example, the same timing values as used in the above example show the impact on a system with a four-fold increase in parallelism:TPgm/Vfy=4*TX+TPRG+TRD+4*TX=526.4 μsMaking the data verification time 24% of the overall four-page copy operation.